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Verification Engineer

Microgreen Technologies LLCAustin, TX🇺🇸United States

Quick overview

SeniorityMid Senior
Work modeOn Site
LocationAustin, TX, United States
Verilog

Job description

Title - Verification Engineer 4

Location: Austin, TX (Onsite)

PREFERRED EXPERIENCE:

  • Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)
  • Strong proficiency in System Verilog Assertions (SVA) and formal property specification
  • Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
  • Familiarity with scripting languages (TCL, Python, Perl) for flow automation
  • Extensive experience in design verification with a strong focus on formal verification
  • Expertise in System Verilog and UVM-based verification methodologies - Nice to have

Comments for Suppliers:

  • Formal verification - use of Jasper or VC formal tools, Able to write/debug formal properties, have hands-on FPV or SEQ, hands-on atleast 3-5 yrs on the above requirements.

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