ASIC Engineering Technical Leader

SDH Systems is hiring ASIC Engineering Technical Leader with Min 12+ Years of experience with a focus on Design-for-Test and can lead the development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products.

Job Title: ASIC Engineering Technical Leader

Location: San Jose , CA

Interview Process: Video

Work Schedule: Onsite

Job Description:

We are seeking a motivated, proactive, and intellectually curious ASIC Engineering Technical Leader with a focus on Design-for-Test. In this role, you will lead the development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products.

Lead the implementation of SSN-based test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent tools for RTL and gate netlist DFT implementation.

Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post-silicon testing and validation support

Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools

Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems

Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations

Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Preferred Qualifications

12+ years of experience working with ASICs

10+ years of experience in scan insertion and DFT setup, integration and validation

5+ years of experience in SSN

Experience driving ASIC DFT execution from concept through tapeout

Experience working with ATE testers and test teams

RTL experience to understand and debugging issues pertaining to DFT

Ability to solve complex problems including clock domain crossings

Familiar with advanced silicon process and technology nodes for high speed and low power consumption

Strong implementation or integration of design blocks using Verilog/System Verilog