Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
United States
Posted
21 hours ago
GitPython
Job Description
- Integrate and configure IPs using FlexNoC for AXI, DDR, PCIe, and other interconnect architectures.
- Develop and refine microarchitecture and infrastructure components for SoC-level integration.
- Write, optimize, and maintain SystemVerilog RTL for IP and top-level design.
- Perform timing closure using Synopsys PrimeTime and ensure sign-off quality results.
- Conduct synthesis using Synopsys Design Compiler, optimizing area, performance, and power.
- Run and debug LINT and CDC checks to ensure high-quality, clean RTL.
- Collaborate cross-functionally with design, verification, and physical design teams.
- Develop automation scripts in Python to streamline design, build, and verification flows.
- Manage version control and collaboration using Git/GitHub.
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