HBM PHY System Architect

Qualcomm seeks an HBM PHY System Architect to define and optimize high-bandwidth memory physical layer architectures for next generation wireless, AI, and multimedia SoCs. You will own HBM PHY system definition, link budgets, signaling, timing, power and thermal trade offs, and integration with digital controllers and package/board design. Collaborate with analog/mixed signal, RTL, signal integrity, and packaging teams to drive specifications, modeling, and validation strategies. Develop system level simulations, support silicon bring up, and guide design for manufacturability and reliability in a fast paced, innovation driven environment.

Responsibilities

• Define HBM PHY system architecture, interfaces, and performance requirements for advanced So
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• Develop link budgets, timing, power, and signal integrity requirements for HBM interfaces
• Collaborate with analog/mixed signal, RTL, SI/PI, and packaging teams on end to end PHY design
• Create and maintain HBM PHY specifications, documentation, and design guidelines
• Build and run system level models and simulations to validate architecture and margins
• Support floorplanning, package/board design, and routing constraints for high speed HBM links
• Guide silicon bring up, debug, and characterization of HBM PHY in lab and production
• Drive design for manufacturability, reliability, and yield for high volume deployment
• Track HBM standards evolution and benchmark competitive solutions to inform roadmaps
• Collaborate with cross functional global teams to deliver on schedule and quality targets

Required Skills

• HBM PHY architecture
• High speed memory interfaces
• Signal integrity (SI)
• Power integrity (PI)
• Link budget and timing analysis
• System level modeling and simulation
• Analog/mixed signal and RTL interaction
• Package and PCB high speed design
• Silicon bring up and validation
• JEDEC HBM standards