Why This Role Stands Out
This hybrid Verification Engineer role offers significant career growth and the chance to develop advanced formal verification skills with cutting-edge tools. You'll thrive here if you have a strong background in System Verilog Assertions and formal verification methodologies, contributing to a reputable company with excellent flexibility. Apply today to advance your engineering career!
Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
Sunset Valley, TX, United States
Posted
20 hours ago
Verilog
Job Description
Job Description:
- Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)
- Strong proficiency in System Verilog Assertions (SVA) and formal property specification
- Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
- Familiarity with scripting languages (TCL, Python, Perl) for flow automation
- Extensive experience in design verification with a strong focus on formal verification
- Expertise in System Verilog and UVM-based verification methodologies - Nice to have
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