Physical Design Engineer

Title: Physical Design Engineer

Location: Santa Clara CA/ San Diego CA/ Austin TX / Chandler AZ

Minimum Qualifications

• Bachelor’s degree in Electrical/Electronics Engineering, VLSI, Computer Engineering, or a related field with 3+ years of hands-on experience in ASIC Physical Design.

  (OR Master’s degree with 2+ years of relevant experience; OR PhD with 1+ year of experience)

• Proven track record of taking complex blocks through full Netlist-to-GDSII flow to successful tape-out.

• Hands-on proficiency with industry-standard EDA tools:

  • P&R: Cadence Innovus or Synopsys ICC2

  • Timing/STA: Synopsys PrimeTime or Cadence Tempus

  • Physical Verification: Siemens Calibre (DRC/LVS)

  • Power Integrity: Ansys RedHawk or Cadence Voltus

  • Equivalence Checking: Synopsys Formality or Cadence Conformal (LEC/CLP)

• Solid understanding of timing closure fundamentals (setup, hold, clock skew, jitter, OCV/AOCV/POCV).

• Strong scripting skills in Tcl and Perl/Python.

Preferred Qualifications

• Experience with advanced FinFET/GAA process nodes (7nm, 5nm, 4nm, 3nm, or 2nm).

• Experience implementing high-speed CPU/GPU cores, DSPs, or high-bandwidth memory interfaces (LPDDR, PCIe).

• Deep understanding of deep sub-micron effects, RC extraction, multi-patterning, and DFM rules.

• Proven track record of optimizing designs for aggressive PPA (Power, Performance, Area) targets.

• Strong debugging, analytical, and problem-solving abilities with solid written and verbal communication skills.