Haystack
← Back to Jobs
Engineering
AS

Opening for Design Verification Engineer, Principal - CA

Aptuity Solutions, IncSanta Clara, CA🇺🇸United StatesPosted 17 Jul 2026

Why This Role Stands Out

This Principal Design Verification Engineer role offers a significant opportunity to lead complex SOC tape-outs and shape cutting-edge verification methodologies within a reputable company. You'll thrive here if you possess extensive experience in SystemVerilog, UVM, and leading verification teams, and are looking for a hybrid work environment that fosters growth and innovation. Apply to leverage your expertise and drive impactful projects in Santa Clara.

Quick Overview

Seniority
Leader
Work mode
Hybrid
Location
Santa Clara, CA, United States
Posted
2 months ago
Verilog

Job Description

We have opening for Design Verification Engineer, Principal

Location - Santa Clara, CA

Full time permanent position

Sponsorship available

Must-haves
BS Computer Engineering, Electrical Engineering, or Computer Science
10+ years of verification and firmware and software development experience (or MS/PhD 5+ years experience).
Proven track records of leading Design Verification implementation activity
Tape-out of complex SOC under tight schedule.
In depth understanding and experience with System Verilog, UVM.
In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
Experience with scripting language such as Python or Perl and EDA Verification tools.
Experience with Object-Oriented Design and implementation.
Good understanding of Linux O.S.
Good programming skills desired, especially C++ and ARM assembly.
Understanding of networking protocols, a plus.
Other Skills:
Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
Requires the ability to accept and work with differing opinions.
Cannot be a close-minded developer.
Must be able to learn on the fly and work in a fast-paced environment.
Required Skills
Proven track records of leading Design Verification implementation activity.
Tape-out of complex SOC under tight schedule.
In depth understanding and experience with System Verilog, UVM.
In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
Experience with scripting language such as Python or Perl and EDA Verification tools.
Experience with Object-Oriented Design and implementation.
Good understanding of Linux O.S.
Good programming skills desired, especially C++ and ARM assembly.
Preferred or Nice-to-have Skills
Understanding of networking protocols, a plus.
Years of Experience: 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).
Industry Experience: Semi
Education Requirements: BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).

Similar jobs