LEAD ASIC DFT STAFF ENGINEER – REMOTE

Hiring: Lead ASIC DFT Staff Engineer

Location: Remote – PST Time Zone

Experience: 10+ Years

We are looking for a Lead/Staff ASIC DFT Engineer with strong hands-on experience in end-to-end Design-for-Test (DFT) for complex ASIC/SoC designs.

Required Skills:
• SCAN / Scan Insertion / Scan Architecture / Scan Compression
• ATPG / ATPG Simulation / Fault Coverage / Diagnosis
• MBIST / LBIST / SMS
• TetraMAX / TMAX / DFTMAX
• Tessent
• DFT DRC / Debug
• Pattern Retargeting / Pattern Porting
• SDF / SDC / DFT Timing / Timing Simulation
• Post-Silicon Validation / Silicon Bring-Up / Debug
• JTAG / Boundary Scan / iJTAG / SSN
• IP-Level & Hierarchical DFT
• TCL / Perl / Python

Additional Requirements:
• Strong experience with Synopsys, Cadence, and Siemens/Mentor DFT tools
• Experience with large ASIC/SoC designs and multi-domain DFT integration
• Good understanding of RTL, Synthesis, LEC, STA, PLLs, and Physical Design
• Strong failure analysis, root-cause investigation, and silicon debug experience