Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
Santa Clara, CA, United States
Posted
18 hours ago
Job Description
- 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
- Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
- Proven expertise in ATPG pattern generation, analysis, and debug
- Experience with MBIST, including memory test architectures and diagnostics
- Knowledge of IO Test methodologies for interface and pin level validation
- Solid understanding of clock DFT and clock verification concepts
- Strong grasp of digital design and RTL fundamentals
- Experience with industry standard DFT/ATPG EDA tools
- Ability to work effectively in fast paced, high performance semiconductor programs
- Strong analytical, problem solving, and communication skills
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