Physical Design Engineer

Title: Physical Design Engineer

Location: Palo Alto, CA (Full Onsite)

 
Employment Eligibility Statement
Due to specific project and client requirements, this position is open to U.S. Citizens and U.S. Lawful Permanent Residents (s) . Sponsorship is not available at this time. Danta Technologies evaluates all candidates in compliance with the Immigration and Nationality Act (INA) and EEOC guidelines . All hiring decisions are made without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, or any other protected characteristic.

JD for PD:

• Exposure to TSMC 2NP/3NP is must
• Perform end‑to‑end physical design flow:
• Floor planning
• Power planning (PG grid, IR)
• Placement & optimization
• CTS (Clock Tree Synthesis)
• Routing
• Post‑route optimization
• Achieve timing closure across all modes and corners
• Resolve DRC, LVS, ERC and signoff violations
• Handle low‑power design techniques:
• Multi‑Vt, Multi‑voltage (UPF)
• Power gating, clock gating
• Perform physical verification and signoff:
• STA (Primetime)
• SI / Crosstalk
• IR drop & EM analysis
• Work on advanced nodes (7nm, 5nm, 3nm or below)
• Collaborate with:
• RTL & Micro‑architecture teams
• DFT & Test engineers
• Foundry and CAD teams
• Debug complex timing, congestion, power, and variability issues
• Drive methodology improvements and automation (scripts/flows)