Design For Test Engineer IV (IC)

Design For Test Engineer III (IC) | San Jose, CA | On-site | $95,900.00 - $170,500.00

This employer is a leading global provider of product engineering and semiconductor design services, fueling technological innovations across multiple verticals. With a strong history of developing successful products and expansive global reach, they offer a dynamic environment for skilled engineers to contribute to cutting-edge projects. They are committed to accelerating connected products innovation for a vast client base.

The Role

• Implement Design For Test (DFT) for advanced networking chips (3nm and 5nm) and IP DFT work.
• Conduct RTL checks for scan-insertion compatibility using Synopsys Spyglass.
• Perform scan-insertion using Tessent TestKompress and ATPG pattern generation.
• Execute pattern simulations (with and without timing) and debug mismatch issues using Verdi.
• Develop and enhance DFT flows using scripting languages (Perl, Shell, TCL) and Makefile automation.
• Perform MBIST and IEEE 1149.1 JTAG insertion, verification, and silicon debug.

What You'll Need

• 5-7 years of experience in DFT.
• Proficiency in scan-insertion, ATPG, GLS, and pattern simulations.
• Experience with MBIST and IEEE 1149.1 JTAG insertion and verification.
• Strong scripting skills in Perl, Shell, and TCL.
• Experience with multi-million gate count SoCs in Networking, Consumer, and various IPs (e.g., PLL, Serdes).
• Familiarity with Low Power DFT concepts.

What's On Offer

• Competitive salary range: $95,900.00 - $170,500.00.
• Comprehensive benefits package including Medical, Dental, Vision Insurance, and 401k with matching contributions.
• Opportunities for professional growth and tuition reimbursement.
• Dynamic work environment with exposure to advanced semiconductor technologies.

Apply via Haystack today!