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Full timeTechnology

Design For Test Engineer IV (IC)

Arrow Electronics, Inc.San Jose, CA🇺🇸United States

Why this role stands out

This role offers an exceptional opportunity to work on cutting-edge 3nm and 5nm networking chips, developing valuable expertise in advanced DFT implementation and ATPG pattern generation. You'll thrive here if you have 5-7 years of DFT experience and a passion for problem-solving using industry-leading tools like Mentor Tessent, Synopsys Tetramax, and VCS. Embrace this chance to elevate your career in a dynamic engineering environment.

Quick overview

SeniorityMid Senior
Employment typeFull Time
Work modeOn Site
LocationSan Jose, CA, United States
ShellPerl

Job description

Design For Test Engineer III (IC) | San Jose, CA | On-site | $95,900.00 - $170,500.00

This employer is a leading global provider of product engineering and semiconductor design services, fueling technological innovations across multiple verticals. With a strong history of developing successful products and expansive global reach, they offer a dynamic environment for skilled engineers to contribute to cutting-edge projects. They are committed to accelerating connected products innovation for a vast client base.

The Role

  • Implement Design For Test (DFT) for advanced networking chips (3nm and 5nm) and IP DFT work.
  • Conduct RTL checks for scan-insertion compatibility using Synopsys Spyglass.
  • Perform scan-insertion using Tessent TestKompress and ATPG pattern generation.
  • Execute pattern simulations (with and without timing) and debug mismatch issues using Verdi.
  • Develop and enhance DFT flows using scripting languages (Perl, Shell, TCL) and Makefile automation.
  • Perform MBIST and IEEE 1149.1 JTAG insertion, verification, and silicon debug.

What You'll Need

  • 5-7 years of experience in DFT.
  • Proficiency in scan-insertion, ATPG, GLS, and pattern simulations.
  • Experience with MBIST and IEEE 1149.1 JTAG insertion and verification.
  • Strong scripting skills in Perl, Shell, and TCL.
  • Experience with multi-million gate count SoCs in Networking, Consumer, and various IPs (e.g., PLL, Serdes).
  • Familiarity with Low Power DFT concepts.

What's On Offer

  • Competitive salary range: $95,900.00 - $170,500.00.
  • Comprehensive benefits package including Medical, Dental, Vision Insurance, and 401k with matching contributions.
  • Opportunities for professional growth and tuition reimbursement.
  • Dynamic work environment with exposure to advanced semiconductor technologies.

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