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Physical Design Engineer

Reveille TechnologiesMountain View, CA🇺🇸United StatesPosted 13 Jul 2026

Why This Role Stands Out

Advance your career in cutting-edge chip design as a Physical Design Engineer at Reveille Technologies, where you'll optimize PPA and achieve timing closure on advanced nodes. This hybrid role is perfect for experienced engineers with strong problem-solving skills ready to collaborate with cross-functional teams and contribute to impactful silicon innovations. You'll thrive in a dynamic environment with excellent opportunities for professional growth.

Quick Overview

Work Type
Hybrid
Level
Mid Senior

Job Description

Hi,

Job Title: Physical Design Engineer (PnR / PPA / Timing Closure)
Location : Mountain View, CA

Responsibilities:


We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Preferred Qualifications:

  • Bachelor's or Master's degree in Electrical/Electronics Engineering.
  • Experience in advanced nodes (7nm/5nm/3nm preferred).
  • Strong debugging and problem-solving skills.
  • Experience working with cross-functional silicon teams.

    Thanks & Regards..,

    Arun Prasath


    Reveille Technologies, Inc

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