DFT Engineer

Job Title: DFT Engineer

Location: Saratoga, CA (Onsite)

Duration: Contract & Full-Time

Job Description:

• Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG).
• Proficiency in Synthesis design constraints. ( Ie SDC)
• Prior experience with Serializers/Deserilizers.
• Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis,
• Define and implement OCC. Exposure to advanced DFT techniques like LBIST and streaming preferred.
• Fluent in RTL level and Gate level simulation.
• Supervise ATPG generation and achieve high coverage goals for scan and @speed scan.

Qualifications:

• Knowledge using synthesis, DFT & Simulation CAD tools
• Familiarity with logic & physical design principles to drive low-power & higher-performance designs
• Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL
• Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
• Prior Exposure to EMIB architectures and bridge is a plus.
• Knowledge of Verilog and System Verilog
• Prior experience of multiple tape out in deep submicron 7nm or below.