Why This Role Stands Out
This hybrid DFT Engineer role at VGAI Solutions Inc. offers a fantastic opportunity for experienced engineers to deepen their expertise in scan insertion and ATPG validation using industry-leading tools, contributing to cutting-edge semiconductor solutions. If you thrive in a collaborative environment with significant career growth potential and enjoy a balanced work-life, this position is an excellent next step for your career journey. Apply today to join a reputable company and make a real impact!
Quick Overview
Job Description
Looking for a senior DFT Engineer with 8–12 years of relevant experience in Scan Insertion and ATPG Validation, with hands-on experience using Mentor Tessent and Synopsys DFT Compiler.
DFT Scan Insertion / ATPG Validation Engineer
Location: Santa Clara, CA
Duration: 12 Months
Experience: 8–12 years
Required Skills:
- Strong experience in DFT Scan Insertion
- Hands-on experience with ATPG Validation
- Strong understanding of DFT methodologies, scan architecture, and ATPG flows
Required Tools:
- Mentor Tessent (Siemens)
- Synopsys DFT Compiler
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