Why this role stands out
Accelerate your career at FSTONE Technologies by driving cutting-edge ASIC/SoC designs for a world-leading organization while enjoying the flexibility of a hybrid work environment. This role is perfect for a collaborative engineer who thrives on solving complex PPA challenges and wants to make a high-impact contribution within a talented, high-performing silicon engineering team. Apply today to take the next step in your professional journey and help shape the future of technology.
Quick overview
Job description
We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle.
Key Responsibilities
· Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals
· Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution
· Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation
· Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency
· Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence
· Support timing closure by identifying implementation bottlenecks and recommending design improvements
· Participate in design reviews and contribute to continuous process and methodology improvements
Required Qualifications
· Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
· Strong hands-on experience in ASIC/SoC physical design with 10+ years of industry experience.
· Expertise in RTL synthesis and timing optimization
· Solid experience with floorplanning for advanced technology nodes
· Strong understanding of netlist optimization and physical implementation methodologies
· Experience collaborating with RTL/design teams to improve design quality and implementation efficiency
· Excellent communication and cross-functional collaboration skills
Preferred Skills
· Experience with industry-standard EDA tools for synthesis and physical design
· Strong understanding of timing, congestion, power, and area optimization techniques
· Experience working on high-performance CPU, GPU, AI/ML, or networking SoCs is a plus
If you are looking for a new project, Please send your resume to abhishek at fstonetechnologies dot com
Regards
Abhishek Mishra
FSTONE Technologies
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