Verification Engineer

Hello,

Title :: Verification Engineer

Location :: San Jose, CA

Job Type- Fulltime

Below is the job description ::

• Test bench development using System Verilog UVM.
• Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections.

Requirements:

• 10+ Design Verification experience.
• Deep knowledge about System Verilog, UVM and verification coverage matrix.
• Strong experience with PCIe.
• Very familiar with the peripheral protocols such as UART, I2C, SPI Flash.
• Proficient in Python or Perl scripting.
• Programming experience with C/C++.