Design Verification Engineer

Hi,

Full Time / Permanent Role 

Job Title: Design Verification Engineer
Location : San Jose , CA & Austin , TX : Onsite

Required Qualifications:   Protocols - PCIe, Ethernet, die-to-die / chip-to-chip, HBM, DDR

• Experience handling vendors and integration of IP/VIP’s
• UVM/System Verilog

Thanks & Regards..,

Arun Prasath