Design Verification Lead

Design Verification Lead 

Experience: 8+ Years

Location:  San Jose/Portland USA

 Position Summary

 We are looking for a highly motivated Design Verification Lead with strong expertise in SystemVerilog/UVM-based verification of complex memory subsystems. The candidate will be responsible for driving verification of high-performance memory architectures involving AXI4 interconnects, HBM interfaces, buffer management schemes, transaction scheduling, and high-throughput data movement engines.

The ideal candidate should have extensive experience in subsystem-level verification, verification closure, performance validation, and debugging of complex scenarios involving a large number of concurrent outstanding memory transactions.

 Key Responsibilities

 Lead verification activities for memory-intensive SoC subsystems and AI accelerator architectures.

Develop comprehensive verification plans, test strategies, and coverage models.

Architect and implement reusable SystemVerilog/UVM verification environments.

Verify complex AXI4-based subsystems including: 

Multi-master/multi-slave configurations

Outstanding transaction handling

Out-of-order completions

QoS and arbitration mechanisms

Bandwidth and latency validation

Verify HBM memory interfaces and high-bandwidth memory access traffic patterns.

Develop stimulus and checkers to validate: 

Large numbers of pending memory transactions

Read/write ordering

Backpressure handling

Buffer overflow/underflow conditions

Performance corner cases

Verify memory buffer management algorithms and data movement engines.

Validate optimized scheduling and arbitration logic for throughput, fairness, and latency requirements.

Develop protocol compliance checkers, scoreboards, assertions, and functional coverage models.

Drive regression execution, failure analysis, coverage closure, and verification signoff.

Collaborate closely with Architecture, RTL Design, Performance Modeling, Firmware, and Validation teams.

 Required Qualifications

 Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

Minimum 8+ years of Design Verification experience in ASIC/SoC development.

Strong expertise in: 

SystemVerilog

UVM

Assertions (SVA)

Coverage-Driven Verification

Constrained Random Verification

Extensive hands-on experience building UVM environments from scratch.

Strong subsystem-level verification experience.

Deep understanding of AXI4 protocol including: 

Outstanding transactions

ID-based ordering

Bursts

Interleaving

Performance validation

Protocol compliance checking

 Experience verifying memory subsystems involving: 

 Memory controllers

DMA engines

Buffer managers

Data movement architecture

Good understanding of HBM architecture and interfaces.

Experience verifying high-throughput memory access patterns with large numbers of concurrent pending transactions.

Experience validating schedulers, arbitration logic, and traffic management algorithms.

Strong debugging and root-cause analysis skills.

 Preferred Qualifications

 Experience with HBM2E / HBM3 / HBM3E memory subsystems.

Experience in AI/ML accelerator, networking, or datacenter SoCs.

Knowledge of cache-coherent interconnects and memory hierarchies.

Experience with performance modeling and verification.

Experience with Formal Verification and Assertions.

Experience with Emulation/FPGA acceleration platforms.

Familiarity with Python, Perl, or Shell scripting for automation.

Desired Technical Skills

 SystemVerilog

UVM

AXI4 / AXI4-Stream

HBM2E / HBM3

Memory Controllers

DMA Engines

Buffer Management

Scheduler Verification

Functional Coverage

Assertions (SVA)

VCS / Xcelium / Questa

Python Scripting