Senior ASIC RTL DESIGN Engineer

12 Months + CONTRACT Starting in September

SKILLS:
SENIOR ASIC RTL Design
Verilog
High Speed Memory Interface Experience 
Logic synthesis & Timing constraints
Forward Error Correction (FEC), Bit Rate Error (BER) calculations
Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation

Prefer experience with some of:

• LPDDR5
• UFS/Flash
• PCIe Gen4/5