Why This Role Stands Out
As a Senior ASIC Design Engineer at Reveille Technologies, you'll drive innovation in Network-on-Chip designs, gaining valuable experience in a hybrid environment. This role is perfect for experienced engineers with a strong background in RTL, microarchitecture, and SoC integration who thrive on complex challenges and contributing to cutting-edge semiconductor technology. Apply now to join a dynamic team and advance your career in a leading tech company.
Quick Overview
Job Description
Hi ,
This role is a Full Time / Permanent .
Title: Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer
Location : Mountain View CA
Qualifications
• 8+ years delivering ASIC/SoC IP designs.
• 6+ years of hands-on digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs.
• Experience with NoC/interconnect and high-throughput/low-latency designs.
• Experience with SoC integration, post-silicon debug, and Python scripting.
Key Skills: ASIC | NoC | RTL | SystemVerilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python
Thanks & Regards..,
Arun Prasath
Reveille Technologies, Inc
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