Pre-Layout Synthesis and STA Engineer

Pre-Layout Synthesis and STA Engineer

Key Responsibilities:

1. Perform pre-layout synthesis to optimize digital designs for area, power, and timing.

2. Conduct static timing analysis (STA) to ensure design meets timing constraints.

3. Analyze and resolve timing issues, optimizing design for performance and power.

4. Collaborate with cross-functional teams to ensure design meets requirements.

Requirements:

1. Education: Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.

2. Experience: 5 +years of experience in pre-layout synthesis and STA.

Skills:

- Proficiency in synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).

- Expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).

- Strong understanding of digital design, timing constraints, and optimization techniques.

- Experience with scripting languages (e.g., Tcl, Python).

Nice to Have:

1. Experience with advanced node technologies (e.g., 7nm, 5nm).

2. Knowledge of physical design flow.

3. Familiarity with Agile development methodologies.

What We Offer:

1. Competitive salary and benefits package.

2. Opportunities for professional growth and development.

3. Collaborative and dynamic work environment.