Verification Engineer 5

Job Title: Verification Engineer 5

Job Location: Markham, ON

Job Type: Contract

Job Overview:

Requirement/Must Have:

• 8-10+ years of experience in ASIC, IP, or SoC verification.
• Strong expertise in SystemVerilog, UVM, and constrained-random verification methodologies.
• Proven experience developing verification plans, functional coverage models, coverage-driven verification strategies, and coverage closure.
• Hands-on experience with formal verification methodologies and industry-standard formal verification tools.
• Strong understanding of assertion-based verification (SVA) and formal property development.
• Experience creating reusable verification environments, verification IP, and verification infrastructure.
• Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies.
• Experience with simulation, regression management, coverage analysis, and debug tools.
• Experience working through multiple successful silicon product cycles.
• Strong communication and collaboration skills.
• Bachelor s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• Master s degree preferred.
• DCN IP design verification experience.
• Ability to work on-site at least 3 days per week, with potential for 5 days as needed.

Responsibilities:

• Define and execute comprehensive verification strategies for complex IP and subsystem designs.
• Develop verification plans based on architecture and design specifications.
• Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components.
• Create directed and constrained-random test scenarios to validate functionality, performance, and robustness.
• Develop functional coverage plans and coverage models, and drive coverage closure.
• Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics.
• Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis.
• Develop and maintain assertion-based verification (SVA) infrastructure and verification content.
• Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues.
• Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle.
• Analyze verification metrics and recommend improvements to verification quality and efficiency.
• Contribute to verification methodology development, automation, and continuous process improvement.

Nice to Have:

• Display IP and display subsystem verification.
• Formal verification and assertion-based verification (ABV).
• Functional coverage architecture and coverage closure methodologies.
• Graphics, multimedia, and video processing pipelines.
• Display interfaces and protocols including DisplayPort, eDP, HDMI, and MIPI.
• High-speed interfaces and protocols.
• Memory subsystem verification.
• Experience with AI or AI-assisted engineering tools.

Skills:

• SystemVerilog.
• UVM.
• ASIC Verification.
• SoC Verification.
• Formal Verification.
• SVA.
• Functional Coverage.
• Constrained-random verification.
• Digital Design.
• Computer Architecture.

Qualification And Education:

• Strong problem-solving and analytical skills.
• Ability to work independently and drive technical initiatives.
• Strong verbal and written communication skills.
• Experience leading verification efforts from planning through signoff.
• Commitment to engineering excellence and product quality.

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• Medical, Dental, and Vision Insurance
• 401(k) Retirement Plan
• Health Savings Account (HSA)
• Disability Insurance (Short-Term and Long-Term)
• Life and AD&D Insurance
• Paid Sick Leave (where required by applicable state or local law)
• Supplemental Insurance Plans
• Identity Theft Protection
• Pet Insurance
• Employee Wellness Programs
• Employee Assistance Program (EAP)
• Career Growth and Professional Development Opportunities