Formal Veification Engineer

Job Title: Formal Verification Engineer
Interview: Virtual
Job Duration: Long Term Contract
Job Location: Austin, TX OR Bay Area, CA
Job Description

We are seeking experienced Formal Verification Engineers to verify complex RTL designs using formal methodologies and ensure functional correctness before tape-out. The ideal candidate will have strong hands-on experience with SystemVerilog Assertions (SVA), formal property checking, equivalence checking, and formal verification tools.

Key Responsibilities

• Develop formal verification strategies for RTL designs.
• Create assertions and properties using SystemVerilog Assertions (SVA).
• Develop formal test plans and verification environments.
• Perform property checking and equivalence checking.
• Debug formal counterexamples.
• Identify and resolve RTL/design issues.
• Collaborate closely with RTL designers and verification teams.
• Support formal verification sign-off.

Required Skills

• Strong Formal Verification experience.
• Proficiency in SystemVerilog and SVA.
• Hands-on experience with Synopsys VC Formal, Cadence JasperGold, or equivalent.
• Strong understanding of RTL.
• Strong knowledge of assertions and formal methodologies.
• Experience debugging complex counterexamples.

Preferred Skills

• Experience with equivalence checking.
• Experience with CDC/RDC verification.
• CPU/SoC/IP verification experience.
• Advanced semiconductor design experience.