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DFx Verification Engineer

Exl Neo TechnologiesSanta Clara, CA🇺🇸United StatesPosted Sep 18, 2026

Why This Role Stands Out

This DFx Verification Engineer role at Exl Neo Technologies offers a fantastic opportunity to contribute to cutting-edge projects and develop your expertise in a reputable company. You'll thrive here if you're a seasoned engineer eager to make a significant impact and grow your career in a collaborative environment. Apply now to explore this exciting prospect!

Quick Overview

Seniority
Mid Senior
Work mode
On Site
Location
Santa Clara, CA, United States
Posted
2 weeks ago
Verilog

Job Description

DFx Verification Engineer

Location: - Santa Clara, CA (Onsite)

Exp Range: - 5-20 Years of experience

Long Term Contract (12 Months +) / Full Time Position

JD

Key Responsibilities

  • Develop and execute verification plans for DFx features including:

  • Scan (stuck-at, transition fault)
  • MBIST / LBIST
  • Boundary Scan (JTAG)
  • Memory repair and redundancy
  • Low-power test scenarios

  • Create and maintain testbenches using SystemVerilog/UVM for DFx validation
  • Verify:
    • Scan chain integrity and connectivity
    • Test mode functionality and coverage
    • ATPG pattern validation and debug
    • BIST controllers and memory test logic

Technical Skills

  • Strong knowledge of:

  • DFT concepts (Scan, ATPG, MBIST, JTAG)
  • Digital design fundamentals

  • Expertise in:

  • System Verilog and UVM
  • Simulation tools (VCS, Xcelium, Questa)

  • Familiarity with:

  • ATPG tools (TetraMAX, Modus, FastScan)
  • Debug tools (Verdi, DVE)

  • Understanding of:

  • Low-power design (UPF/CPF)
  • Clocking and reset strategies

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