FPGA/Embedded Hardware Design Engineer with Security Clearance

Description SAIC is seeking an experienced FPGA/Embedded-Systems Engineer to design, verify, and integrate advanced digital processing architectures. The ideal candidate will possess strong FPGA development experience using VHDL and Verilog, along with embedded software skills and a deep understanding of digital signal processing, timing closure, and Linux-based workflows. This role requires the ability to solve complex technical problems and deliver robust production-ready designs.

Qualifications Key Responsibilities

• Develop FPGA architectures using VHDL-2019, VHDL-2008, VHDL, and basic Verilog as required.
• Design solutions targeting Xilinx UltraScale+ MPSoC devices; experience with Versal devices is a strong plus.
• Create self-checking simulation constructs and testbenches to validate functional and corner-case behavior.
• Script simulation, synthesis, and implementation workflows using Tcl and shell scripting to automate toolflows.
• Implement high-throughput streaming data paths, including FIFO structures, CDC mechanisms, circular buffers, clocking architectures, and timing constraints.
• Perform FPGA debug through HDL simulation, waveform analysis, hardware debugging, and logic analyzer tools.
• Develop and debug embedded software in C, C++, Python, and related languages to interface with FPGA logic.
• Contribute to DSP algorithm design when needed, depending on project requirements.
• Work with SDR platforms such as Ettus USRP, Epiq Matchstiq, and Pluto SDR to support system-level development.
• Apply knowledge of microcontroller firmware design for supporting embedded subsystems.
• Develop on Linux systems and write automation scripts using Bash.
• Use Xilinx Vivado and Vitis toolchains including Hardware Manager, IP Integrator, IP packaging, and XSim simulation.
• Simulate HDL using tools such as Aldec Riviera Pro and ModelSim for detailed design verification.
• Build customized embedded Linux distributions for MPSoC and Versal devices using Yocto.
• Set up and debug FlexLM license servers as part of maintaining development environments.
• Leverage AI/ML code assistants to enhance development efficiency when appropriate.
• Use Git for version control and collaborative software and FPGA development.

Required Education: Bachelors and fourteen (14) years or more experience; Masters and twelve (12) years or more experience; PhD or JD and nine (9) years or more experience.

• Additional experience may be substituted for a degree Clearance Requirement:
• Must be a U.S. citizen with an active TS/SCI with Polygraph level clearance Target salary range: $200,001 - $240,000. The estimate displayed represents the typical salary range for this position based on experience and other factors.