Senior Verification Engineer

Our client is a highly successful British technology company renowned for designing innovative computing platforms used by millions of developers, educators, engineers, and hobbyists worldwide. With a strong focus on accessible and high-performance computing, the company has established itself as a global leader in embedded and edge computing technologies. As they continue to invest in the development of next-generation silicon platforms, they are expanding their in-house ASIC capability to support an exciting product roadmap.

This role would suit someone who enjoys working autonomously with like minded people. They have an excellent leadership team and working culture. The Opportunity
As a Verification Engineer, you will take ownership for IP and chip level verification planning and execution, and will be constantly interacting with the design team, composing detailed verification plans and creating test benches from scratch or using shared verification components.

Requirements
Hands-on experience with at least three projects
Experience of creating test benches from scratch, using Systemverilog, Python, or UVM
Experience of writing embedded C, ideally for Cortex M-class MCUs
Good technical understanding in at least one complex IP protocol,e.g. PCIe, HDMI, USB, SDIO, AMBA bus architectures
Ability to write functional coverage and SVA
Good understanding of design/front-end processes
Experience with low-power simulations
SoC verification concepts: memory caches, DMA, security architecture (TrustZone or equivalent).

Experience of Cadence simulation tool flow including gate-level simulation. Scripting languages: Bash, TCL, Make, YAML, etc. Please note that this role is based in Cambridge and requires full-time onsite attendance. This opportunity offers a fantastic compensation package and a number of non-monetary benefits. This is a great opportunity to join them as they leap into their next growth phase. For more information, please contact Rachel Mason at IC Resources