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Sr. Semiconductor Package Design Engineer

Oxford Global ResourcesBoxborough, MA🇺🇸United StatesPosted Sep 28, 2026

Why this role stands out

This role offers a fantastic opportunity to drive innovation in high-performance semiconductor packaging, contributing to cutting-edge technology development. You'll thrive here if you possess a strong foundation in substrate design, layout, and signal/power integrity, with a passion for detailed analysis and problem-solving. Apply now to join a dynamic engineering team and advance your career in a critical industry.

Quick overview

SeniorityMid Senior
Work modeOn Site
LocationBoxborough, MA, United States
Posted3 weeks ago
ANSYS

Job description

Job Title: Sr. Semiconductor Package Design Engineer
Location: Boxborough, MA - Onsite
Duration: 12 months; potential for extension based on project needs
Target Start Date: ASAP / based on candidate availability
Job Description:
We are seeking a Sr. Semiconductor Package Design Engineer with extensive experience designing and analyzing IC package substrates for high-performance semiconductor applications. This individual will support package development from early architecture and requirements definition through physical substrate layout, electrical model extraction, analysis, and final design completion.
The ideal candidate combines hands-on semiconductor package substrate design and layout with strong signal-integrity and power-integrity fundamentals. Experience with Ansys HFSS or related Ansys electromagnetic-analysis tools is highly preferred.
Key Responsibilities:
Lead and perform hands-on semiconductor package substrate design and layout while ensuring packages meet signal-integrity, power-integrity, and electrical-performance requirements. Support package architecture decisions, electrical model extraction, analysis, and design progression from initial requirements through final completion.
Required Experience:
10+ years of semiconductor / IC package design, package substrate layout, or closely related experience
Hands-on semiconductor package substrate physical design and layout
Experience with signal integrity, power integrity, and electrical model extraction for semiconductor packages or high-speed interconnects
Experience defining or working with bump maps, ball maps, layer stack-ups, package substrates, or similar IC-package structures
Preferred / Standout Experience:
Ansys HFSS or other Ansys electromagnetic-analysis experience — strong preference
Advanced semiconductor package experience involving 2.5D/3D packaging, interposers, chiplets, RDL/fan-out, or other high-performance package technologies
Experience taking multiple semiconductor package designs from architecture through layout, analysis, and design release

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