Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
Austin, TX, United States
Posted
21 hours ago
Verilog
Job Description
Senior Emulation Engineer
Experience: 6+ Years
Location: Fremont/Bay Area, CA/ Austin, TX
Duration: Long Term
Job Description:
- 6+ years of experience in hardware emulation, pre-silicon validation, or SoC verification.
- Hands-on experience with Cadence Palladium, Siemens Veloce, or Synopsys ZeBu.
- Develop and debug emulation environments for complex SoC/IP designs.
- Experience with platform bring-up, compilation, partitioning, debugging, and performance optimization.
- Strong knowledge of timing closure, timing analysis, and RTL debugging.
- Experience with PCIe and USB subsystem validation/debugging.
- Hands-on experience with Verilog/SystemVerilog.
- Scripting experience in Python, Tcl, or Perl.
- Experience in pre-silicon validation and hardware/software co-verification.
- Collaborate with RTL, verification, firmware, and system validation teams.
- Strong debugging, analytical, and problem-solving skills.
- Bachelor's/Master's degree in Electronics, Electrical, Computer Engineering, or related field.
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