Physical Design Engineer

Position: Physical design engineer

Location: San Jose, CA (onsite)

Job type: Contract

JOB DESCRIPTION:

Key Responsibilities

• Perform RTL synthesis, physical synthesis, floor planning, placement, clock tree synthesis (CTS), routing, and physical implementation.
• Drive timing closure, setup/hold optimization, and signal integrity improvements.
• Optimize power, performance, and area (PPA) across the physical design flow.
• Perform timing analysis, timing correlation, and constraint validation using SDC.
• Work on congestion analysis, high-fanout optimization, clock optimization, and design-rule closure.
• Collaborate with RTL, synthesis, STA, DFT, and verification teams to resolve design issues.
• Analyze and resolve physical design challenges at advanced technology nodes.
• Support full-chip integration, signoff, and tapeout activities.
• Debug implementation issues and ensure design quality, performance, and reliability.

Required Skills

• 5+ years of hands-on experience in ASIC/SoC Physical Design.
• Strong experience in synthesis and RTL-to-GDSII implementation.
• Expertise in floorplanning, placement, CTS, routing, and timing closure.
• Hands-on experience with Cadence Genus and Innovus.
• Experience with advanced technology nodes such as N5/N3 or below.
• Strong understanding of STA, setup/hold timing, clocking, congestion, and PPA optimization.
• Experience with multiple successful tapeouts; 3+ tapeouts preferred.
• Strong scripting and debugging skills.