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Static Timing Analysis Engineer

Apetan ConsultingSan Jose, CA🇺🇸United StatesPosted Oct 8, 2026

Why This Role Stands Out

This role offers a fantastic opportunity to deepen your expertise in static timing analysis within a reputable consulting firm, working on complex SoC designs. If you excel in timing constraints, synthesis, and have experience with industry-standard tools like Synopsys, you'll thrive in this position. Apply today to advance your career in cutting-edge semiconductor engineering.

Quick Overview

Seniority
Mid Senior
Work mode
On Site
Location
San Jose, CA, United States
Posted
3 days ago

Job Description

Position: Static Timing Analysis Engineer

Locations: San Jose, San Diego, Irvine, CA (Onsite)

What You Will Do:

  • Develop and validate timing constraints for intricate SoC designs.
  • Expertise in Synthesis, Equivalency Checking and STA.
  • Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus.
  • Experience with Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA.
  • Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
  • Conduct pre-route timing checks and quality of results (QoR) analysis.
  • Automate timing analysis processes using scripting languages such as Tcl or Perl.
  • Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
  • Ensure compliance with timing signoff checklists and criteria.

What You Will Bring:

  • Experience with high-complexity silicon in advanced technology nodes.
  • Familiarity with timing constraint development for hierarchical designs.
  • Knowledge of clock tree planning and implementation for SoCs.
  • Experience with timing ECO creation and final timing signoff.
  • Proficiency in using STA tools such as PrimeTime, TCM, Tempus and scripting languages such as Tcl, Perl.
  • Proficiency in using synthesis tools (Genus).
  • Must have Full Chip (Top Level), Block Level and Multi-voltage Timing Closure experience.
  • Debug and Fix Timing Issues.
  • This STA engineer needs to do Synthesis, Equivalency Checking and STA.
  • Good understanding of Timing Constraints, Exceptions, CTS and clock constraints, Multi-Mode Multi-Corner timing closure expertise.
  • Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA.
  • Strong understanding of ASIC design flows, including RTL and place-and-route.
  • Excellent problem-solving skills and attention to detail.
  • Effective communication and teamwork abilities.

Education and Experience:

  • Bachelor’s and 8+ years of related experience; at this level post-graduate coursework may be desirable.
  • Master’s degree and 6+ years of related experience.
  • PhD and 3+ years of related experience.

Work Requirements:

  • This role is considered an on-site position located in San Jose.
  • You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.

 

 

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