Design Verification (DV) Lead

Design Verification (DV) Lead (Managerial level )

Fulltime

Sunnyvale, CA, USA Onsite

Visa- G C and U S C only

What You will Do:

Develop functional tests based on verification test plan

•        Drive Design Verification to closure based on defined verification metrics on test

•        plan, functional and code coverage

•        Debug, root-cause and resolve functional failures in the design, partnering with

•        the design/arch team

•        Collaborate with cross-functional teams like Design, Model, Emulation and Silicon

•        validation teams towards ensuring the highest design quality

What You Will Bring:

Experience :10+ years 

•        Experience using constrained-random, coverage driven verification or C/C++

·       verification

•        Experience in verifying a IP block using standard Design Verification (DV) based

·       techniques

•        Experience in Electronic Design Automation (EDA) tools and scripting

·       (Python, Tool Command Language (TCL), Perl, Shell) used to build tools and

·       flows for verification environments

•        Understanding in at least one of the following areas: computer architecture,

·       Central Processing Unit (CPU), Graphics Processing Unit

·       (GPU), networking, interconnects, fabrics or similar designs

•        Experience debugging fails to the line of RTL, closing out bug fixes,

·       using Verdi or equivalent debug tools

•        Experience with revision control systems like Mercurial (Hg), Git or SVN

•        Experience working in a CPU/GPU environment