Staff Custom Analog Layout Engineer

NokiaSan Jose🇺🇸United StatesPosted Jun 2, 2026

Quick Overview

Seniority

Mid Senior

Employment type

Full Time

Work mode

Hybrid

Location

San Jose, United States

Posted

3 months ago

CAD

Job Description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

The successful candidate shall work closely with circuit designers to generate high-quality layout in a highly efficient way. He or she shall utilize advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements. Engaging in high-resolution analog circuit design gives you the chance to create the technical differentiation that will allow Infinera to hold market leadership. By building cutting-edge circuitry, we will together revolutionize the era of efficient high-speed transmission.

NION2026

Work closely with circuit designers to optimize the floor plan;
Perform daily layout editing, DRC/LVS tasks to ensure the quality of the layout;
Employ efficient design methodologies to reduce the number of iterations and promptly deliver the product.

Mandatory Knowledge/Skills/Abilities:

Extremely familiar with layout editing tools, such as Virtuoso and Laker;
Highly proficient with DRC/LVS/ERC related tools and flows, such as Calibre, PVS (or IC Validator);
Decent understanding in the issues of electro-migration and IR drop, RC delay, self-heating, capacitive cross-talk, etc.;
Decent understanding in analog layout requirements, such as matching and shielding;
Has extensive experience in the layout of low-power, high-resolution circuits, such as SD-ADC, SAR-ADC, bandgap, and regulators.
Knowledge in automatic P&R or chip-level floor planning/integration.

Preferred Knowledge/Skill/Abilities:

Decent Understanding of analog design methodologies, including the use of layout constraints;
Knowledge in performing RC extraction and EM/IR analysis;
Excellent communication skills and team spirit to work with members across multiple sites and functionalities;
Experience in designing layouts for high-resolution, high-performance analog / mixed-signal circuits.

Education and Experience Requirements: