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Senior Design Verification (DV) Engineer

Techridge, Inc.San Jose, CA🇺🇸United StatesPosted 6 Aug 2026

Quick Overview

Work Type
Hybrid
Level
Mid Senior

Job Description

We are seeking an experienced Senior Design Verification (DV) Engineer with expertise in SoC/IP verification, SystemVerilog/UVM, and modern verification methodologies. The ideal candidate will lead end-to-end verification activities for IP, Subsystem, and SoC-level designs while collaborating with design, architecture, and cross-functional teams to achieve verification closure.
Key Responsibilities
  • Develop and execute verification plans for IP, Subsystem, and SoC-level designs.
  • Verify SoCs with ARM processors, DSPs, DDR3, and high-speed interfaces.
  • Develop UVM/SystemVerilog-based testbenches and verification environments.
  • Perform constrained-random verification, assertion-based verification, coverage analysis, and debugging.
  • Create and maintain verification scripts using Perl, TCL, and C/C++.
  • Work with industry-standard EDA tools for simulation and verification.
  • Collaborate with design, architecture, and validation teams to ensure verification closure.
  • Support verification of industry-standard protocols including AXI, AHB, PCIe, and memory interfaces.
  • Participate in code reviews, debug complex issues, and improve verification methodologies.
Required Skills
  • 8+ years of Design Verification experience.
  • Strong expertise in SystemVerilog, UVM/OVM, C/C++, Perl, and TCL.
  • Experience with SoC/IP Verification.
  • Strong knowledge of Constraint Random Verification, Assertions (SVA), Coverage Analysis, and Debugging.
  • Experience verifying ARM-based SoCs, DDR3, AXI, AHB, PCI Express, and DSP-based systems.
  • Strong understanding of verification methodologies and EDA tools.
  • Excellent analytical, debugging, and communication skills.
 

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