DV SOC / SoC Design Verification Engineer

Position: DV SOC / SoC Design Verification Engineer Location: Remote Job Type: Contract

Job Summary

We are looking for an experienced SoC Design Verification Engineer to support SoC-level verification, integration, and signoff activities for complex ASIC/SoC designs.

The ideal candidate will have strong hands-on experience with SystemVerilog, UVM, SoC verification, RAL, low-power verification using UPF, Gate-Level Simulation (GLS), and coverage closure. This role will involve integrating IPs/UVCs/VIPs, developing verification environments and testcases, debugging RTL and integration issues, and supporting test-chip validation.

Key Responsibilities

• Develop and execute SoC-level verification plans, testcases, and coverage models.
• Verify subsystem interactions, system functionality, and SoC integration requirements.
• Integrate IPs, UVCs, and VIPs into the SoC-level verification environment.
• Develop and maintain SystemVerilog/UVM-based testbenches.
• Drive functional and code coverage closure and identify coverage gaps.
• Perform power-aware verification using UPF and debug low-power-related issues.
• Execute and debug Gate-Level Simulations (GLS).
• Perform detailed debug of RTL, integration, protocol, and simulation issues.
• Develop and verify RAL (Register Abstraction Layer) models.
• Validate register access, mirroring, prediction, and register-level functional coverage.
• Support test-chip verification and validation
• Collaborate closely with Design, DFT, Firmware, Architecture, and other cross-functional teams to resolve issues and achieve verification signoff.
• Automate verification and debug activities using scripting/programming where required.
• Support verification methodology improvements and contribute to overall SoC verification quality.

Required Qualifications

• Strong hands-on experience with SystemVerilog and UVM.
• Strong experience in SoC-level Design Verification.
• Experience developing and executing verification plans, testcases, testbenches, and coverage models.
• Experience with SoC integration and IP/UVC/VIP integration.
• Hands-on experience with RAL / UVM Register Model and register verification.
• Experience with functional coverage and code coverage closure.
• Hands-on experience with UPF / low-power verification.
• Experience with Gate-Level Simulation (GLS) and GLS debugging.
• Strong RTL and protocol debugging skills.
• Experience with verification automation/scripting.
• Strong communication and cross-functional collaboration skills.

Preferred / Nice-to-Have

• Experience with JTAG verification.
• Experience with DAC or analog/mixed-signal model verification.
• Experience with test-chip verification/validation.
• Experience working with DFT, Firmware, Architecture, and Design teams.
• Experience taking SoC verification through signoff.