ESD Engineer

The ESD Engineer will drive the development of our I/O library—leading the design, simulation, characterization, and validation of advanced I/O pad structures. You’ll define and implement our chip‑ and IP‑level ESD methodology, ensuring every product meets the highest standards of robustness and reliability.

In this role, you’ll design ESD protection devices, create silicon test structures for ESD and latch‑up evaluation, and translate silicon data into optimized design rules. You’ll also collaborate closely with our foundry partners on ESD library updates and LUP rule development.

Success requires a holistic understanding of mixed‑signal CMOS ESD/EOS protection, along with the ability to see gaps, integrate methodologies, and strengthen our end‑to‑end protection strategy. This is a high‑impact opportunity to shape product reliability across Cirrus Logic’s entire mixed‑signal portfolio.