Quick overview
Job description
Qualifications
- Hands-on expertise with commercial test generation tools for large complex designs
- Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST and LBIST
- Experience generating test patterns and analyzing and debugging test failures
- Experience with RTL simulation, synthesis and back end implementation flows
- Experience defining and implementing stuck-at and at-speed techniques
- Experience running test compression flow
- Experience trading off test options with product performance and schedule requirements
- Experience creating and releasing full test programs for device screening
- Test optimization
- Resolve design and flow issues related to DFT, identify potential solutions, and drive execution
Education and Experience
- B.E./B.Tech./M.E./M.Tech in VLSI
- Minimum of 5 years of working experience in DFT flow of a product company.
- Strong fundamentals in digital ASIC design, experience with ASIC test, DFT, and debug
Detailed Responsibilities and Skills
- Define DFT strategy and methodologies
- Define test structures, debug structures, test plans
- Create test vectors, simulate in various modes
- Collaborate with physical design team to close requirements
- Validate DFT requirements are being met
- Work with designers to increase test coverage, debug observability and flexibility
- Verify post-PD designs meet DFT requirements
- Knowledge of full DFT flow (test structure insertion, pattern generation, simulation )
- Hands-on experience with Cadence Genus, Modus tools,
- Should have good understanding of Verilog/VHDL
- Exposure to low power techniques
- Knowledge of TCL and Python scripting is a must
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