Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
United States
Posted
21 hours ago
Microsoft ExcelMicrosoft OfficeMicrosoft PowerPointVerilog
Job Description
ASIC CHIP LEAD
ASIC Design Lead / Senior Chip Design Engineer
What You’ll Do
Architecture and Chip Definition
Lead ASIC architecture development from high-level requirements and block diagrams.
Work with system architects to define chip functionality, interfaces and performance goals.
Write detailed specifications for chip components and subsystems.
RTL Design and Synthesis
Develop RTL designs and run synthesis with Synopsys Design Compiler.
Tune RTL for power, performance and area.
Design, implement and verify complex digital blocks.
Timing Constraints
Create and maintain full-chip timing constraints.
Work with the physical design team to achieve successful place-and-route.
RISC Processor Integration
Constrain and verify embedded RISC processor cores.
Improve processor performance and power efficiency.
Physical Design Support
Support floorplanning, placement and routing with the physical design team.
Resolve design closure issues as they come up.
Verification Support
Partner with verification engineers to confirm functional correctness.
Help build testbenches and validate chip functionality.
Tools and Technical Environment
Modern revision control tools and best practices across a collaborative, multi-site design team.
Strong UNIX/Linux skills, including shell scripting, text utilities (sed, awk, grep) and Modules.
Programming and scripting in C/C++, Perl, Python and TCL.
Comfortable with Microsoft Office and related tools (Word, Excel, PowerPoint, Visio, Project) and PDF conversion.
ASIC Design Lead / Senior Chip Design Engineer
What You’ll Do
Architecture and Chip Definition
Lead ASIC architecture development from high-level requirements and block diagrams.
Work with system architects to define chip functionality, interfaces and performance goals.
Write detailed specifications for chip components and subsystems.
RTL Design and Synthesis
Develop RTL designs and run synthesis with Synopsys Design Compiler.
Tune RTL for power, performance and area.
Design, implement and verify complex digital blocks.
Timing Constraints
Create and maintain full-chip timing constraints.
Work with the physical design team to achieve successful place-and-route.
RISC Processor Integration
Constrain and verify embedded RISC processor cores.
Improve processor performance and power efficiency.
Physical Design Support
Support floorplanning, placement and routing with the physical design team.
Resolve design closure issues as they come up.
Verification Support
Partner with verification engineers to confirm functional correctness.
Help build testbenches and validate chip functionality.
Tools and Technical Environment
Modern revision control tools and best practices across a collaborative, multi-site design team.
Strong UNIX/Linux skills, including shell scripting, text utilities (sed, awk, grep) and Modules.
Programming and scripting in C/C++, Perl, Python and TCL.
Comfortable with Microsoft Office and related tools (Word, Excel, PowerPoint, Visio, Project) and PDF conversion.
What You Bring:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or a related field.
10+ years of hands-on industry experience in ASIC and/or SoC design.
Strong RTL design background in Verilog/SystemVerilog.
Expertise with Synopsys Design Compiler and other industry EDA tools.
Solid grasp of digital design fundamentals.
Working knowledge of RISC architectures such as ARM or MIPS.
A proven history of first-pass silicon success.
Strong problem-solving skills and attention to detail.
A self-starter who is comfortable stepping into technical leadership.
Enjoys mentoring junior engineers.
Works well in a diverse, collaborative team.
Familiar with industry-standard development tools and methodologies.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or a related field.
10+ years of hands-on industry experience in ASIC and/or SoC design.
Strong RTL design background in Verilog/SystemVerilog.
Expertise with Synopsys Design Compiler and other industry EDA tools.
Solid grasp of digital design fundamentals.
Working knowledge of RISC architectures such as ARM or MIPS.
A proven history of first-pass silicon success.
Strong problem-solving skills and attention to detail.
A self-starter who is comfortable stepping into technical leadership.
Enjoys mentoring junior engineers.
Works well in a diverse, collaborative team.
Familiar with industry-standard development tools and methodologies.
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