Why This Role Stands Out
Accelerate your career at Galaxy i Technologies by spearheading high-impact failure analysis and hardware design for cutting-edge hyperscale systems in a flexible hybrid environment. This role is perfect for a seasoned engineer who thrives on solving complex technical challenges and enjoys leading cross-functional teams to drive innovation. Apply today to leverage your expertise in a dynamic, collaborative culture that prioritizes professional growth and technical excellence.
Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
San Jose, CA, United States
Posted
22 hours ago
Job Description
Job Title : Senior Hardware Design & Failure Analysis Engineer
Location : San Jose CA
Hardware Design and Failure Analysis Engineer
Education & Experience: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, or related field with 10+ years of progressive experience in hardware engineering, board design, or system-level failure analysis.
High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).
Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBSVID telemetry, switching noise) and high-speed signal integrity anomalies.
Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.
Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.
Preferred Qualifications
Experience leading hardware quality or reliability taskforces for hyperscale cloud service providers (e.g., Microsoft, Meta, Google, AWS).
Knowledge of advanced packaging technologies (chiplets, 2.5D/3D ICs, CoWoS) and silicon failure mechanisms.
Proficiency in writing custom Python or C automation tools to recreate corner-case/intermittent hardware race conditions.
Skills: EIS : ASIC Ciruit Design - Analog and Mixed Signal IC Circuit design~EIS : Thermal Analysis~EIS : Embedded Digital Hardware Design and Development
Experience Required: 6-8
Education & Experience: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, or related field with 10+ years of progressive experience in hardware engineering, board design, or system-level failure analysis.
High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).
Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBSVID telemetry, switching noise) and high-speed signal integrity anomalies.
Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.
Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.
Preferred Qualifications
Experience leading hardware quality or reliability taskforces for hyperscale cloud service providers (e.g., Microsoft, Meta, Google, AWS).
Knowledge of advanced packaging technologies (chiplets, 2.5D/3D ICs, CoWoS) and silicon failure mechanisms.
Proficiency in writing custom Python or C automation tools to recreate corner-case/intermittent hardware race conditions.
Skills: EIS : ASIC Ciruit Design - Analog and Mixed Signal IC Circuit design~EIS : Thermal Analysis~EIS : Embedded Digital Hardware Design and Development
Experience Required: 6-8
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