Physical Design Engineer (Back-Fill Role)

Job Title: Physical Design Engineer
Location: Mountain View, CA Onsite
Rate: $60-$65/hr. on W2
Openings: 2
Experience: 5 10 Years

Job Overview

We are looking for an experienced Physical Design Engineer with strong hands-on experience in advanced-node SoC physical design, particularly TSMC 3nm/2nm technologies.

The ideal candidate will have experience working on high-performance, low-power SoC/GPU designs and should be capable of owning the physical implementation flow from netlist through GDSII/tapeout.

Key Responsibilities

• Own and execute the complete Netlist-to-GDSII physical design flow for high-performance, low-power SoCs.
• Perform floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, and physical optimization.
• Drive timing closure and resolve setup/hold, congestion, DRC and routing-related issues.
• Optimize designs for Power, Performance, and Area (PPA) at advanced process nodes.
• Work on advanced-node challenges including:
• IR Drop
• Electromigration (EM)
• Crosstalk / Signal Integrity
• Congestion
• Timing violations
• Design Rule violations
• Perform block-level and/or SoC-level physical implementation and optimization.
• Analyze timing and physical design reports and implement appropriate fixes/ECOs.
• Work closely with RTL, STA, DFT, architecture, CAD and verification teams to achieve physical design closure.
• Support physical verification and final signoff activities.
• Contribute to achieving aggressive performance, power, area and tapeout goals.

Required Technical Skills

• 5 10 years of hands-on Physical Design / ASIC / SoC experience.
• Strong experience with Netlist-to-GDSII / RTL-to-GDSII physical design flow.
• Hands-on experience with Cadence Innovus is highly important.
• Experience with one or more advanced process nodes:
• 2nm
• 3nm
• 4nm
• 5nm
• Strong experience in:
• Floorplanning
• Placement
• CTS
• Routing
• Timing Closure
• PPA Optimization
• Physical Design Closure
• Experience with Synopsys Fusion Compiler.
• Strong experience with Synopsys PrimeTime / STA.
• Experience with Calibre for physical verification/signoff.
• Experience dealing with IR Drop, EM, Crosstalk and Signal Integrity issues.
• Experience with high-performance SoC/GPU/ASIC designs is strongly preferred.

Preferred Experience

• Direct experience with TSMC 3nm or 2nm technology.
• Experience with GPU, CPU, AI accelerator, HPC or other high-performance SoCs.
• Proven advanced-node tapeout experience.
• Experience driving aggressive PPA targets.
• Experience with timing ECOs and physical ECOs.
• Strong understanding of advanced-node physical design challenges.