Staff Physical Design Engineer

Required Qualifications:

• Bachelor s/Master s degree in Electrical Engineering or related field
• 8 12 years of experience in ASIC physical design
• Proven experience in full-chip or large block implementation and tapeouts
• Strong expertise in:
• Floorplanning and power planning
• Placement, CTS, routing, and physical verification
• Static Timing Analysis (STA) and timing closure

• Hands-on experience with industry-standard tools such as:

• Synopsys ICC2 / Cadence Innovus
• Synopsys PrimeTime
• Mentor Calibre

• Experience with advanced nodes (7nm and below preferred)
• Strong debugging and problem-solving skills

Preferred Qualifications:

• Experience with low-power design techniques (UPF/CPF)
• Knowledge of EMIR analysis (e.g., Ansys RedHawk-SC)
• Familiarity with multi-voltage designs and power domains
• Experience with high-speed interfaces or complex SoCs (CPU/GPU/AI)
• Exposure to GLS and timing-related silicon debug
• Scripting expertise in Python/TCL