Physical Design Engineer

Physical Design Engineer

Location: Remote
Job Type: Contract

Job Summary

We are looking for an experienced Physical Design Engineer to support block-level implementation and optimization of advanced ASIC/SoC designs. The ideal candidate will have strong hands-on experience across the physical design flow, including floorplanning, placement, CTS, routing, timing closure, ECOs, and tape-out support.

This role is best suited for someone who has worked on complex ASIC designs and is comfortable driving physical design activities while working closely with STA, DFT, RTL, and other design teams.

Key Responsibilities

• Own and execute block-level physical design implementation from floorplan through tape-out.
• Develop and optimize floorplans, macro placement, utilization, and power-aware implementation strategies.
• Perform placement optimization to meet timing, power, area, congestion, and routability
• Drive Clock Tree Synthesis (CTS), routing, optimization, and ECO implementation.
• Perform timing analysis and work toward timing closure and signoff readiness.
• Debug and resolve congestion, utilization, timing, and routing issues throughout the implementation flow.
• Support IR Drop, EM, DFM, and physical verification/signoff
• Work closely with STA, DFT, RTL, and other cross-functional teams to resolve implementation issues.
• Support final tape-out and signoff closure
• Develop and maintain automation scripts using TCL, Perl, and/or Python to improve physical design productivity.
• Analyze implementation results and recommend improvements to achieve PPA and design-quality targets.

Required Qualifications

• Strong hands-on experience in ASIC/SoC Physical Design / Physical Implementation.
• Experience with the complete physical design flow:
  Floorplanning Placement CTS Routing Optimization ECO Signoff/Tape-out.
• Strong hands-on experience with Synopsys Fusion Compiler.
• Solid understanding of timing analysis and timing closure.
• Experience troubleshooting congestion, utilization, routing, and PPA issues.
• Good understanding of LEF/DEF, Liberty, Verilog, and physical design data formats.
• Working knowledge of IR Drop, EM, Physical Verification, and DFM
• Strong scripting/programming skills in TCL, Perl, and/or Python.
• Experience supporting tape-out/signoff
• Strong debugging and problem-solving skills.

Preferred Qualifications

• Experience working on advanced process nodes.
• Experience with full-chip implementation in addition to block-level design.
• Exposure to signoff tools and DFM methodologies.
• Multiple successful ASIC/SoC tape-out
• Experience working with cross-functional RTL, STA, DFT, and physical design teams.