Hiring: Lead Architecture & Performance Modeling Engineer Saratoga, CA | Full-Time

Join a cutting-edge hardware company building next-gen silicon powering large-scale AI networking, training & inference.

We’re looking for a visionary Performance Modeling Leader to define and drive architectural modeling strategy that directly shapes ASIC & SoC design decisions.

Lead high-level performance modeling for networking devices
Partner with ASIC architects & uArch teams on PPA trade-offs
Analyze throughput, latency & bottlenecks to influence architecture
Build scalable modeling frameworks & best practices
Strong expertise in Ethernet, PCIe & networking systems
10+ years experience (MSEE/PhD preferred)
Proficient in C/C++/Python + ASIC/FPGA flows

This is a high-visibility role influencing next-generation AI hardware architecture.