Analog Mixed-Signal SystemVerilog Modeling Engineer

Job Title: Analog Mixed-Signal SystemVerilog Modeling Engineer

Job Location: San Jose, CA

Job Type: Contract

Pay Range: $82.35hr - $86.92hr

Job Overview:

The successful candidate will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog. Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP. The candidate will work closely with analog circuit designers, RTL designers, and verification engineers. The candidate will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.

Responsibilities:

• Reading schematics, netlists, and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Debugging simulation failures and finding the root cause in the model, RTL, or testbench.
• Documenting model behavior, limitations, and interfaces.

EXPERIENCE AND EDUCATION:

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog. Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms. Familiarity with high-speed interface standards is a plus.

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• Medical, Dental, and Vision Insurance
• 401(k) Retirement Plan
• Health Savings Account (HSA)
• Disability Insurance (Short-Term and Long-Term)
• Life and AD&D Insurance
• Paid Sick Leave (where required by applicable state or local law)
• Supplemental Insurance Plans
• Identity Theft Protection
• Pet Insurance
• Employee Wellness Programs
• Employee Assistance Program (EAP)
• Career Growth and Professional Development Opportunities