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Senior ATE Production Test Engineer – SerDes / Co-Packaged Optics (CPO)

VGAI Solutions IncSan Jose, CA🇺🇸United States

Why this role stands out

Advance your career at the forefront of semiconductor innovation by leading production test development for cutting-edge SerDes and Co-Packaged Optics technologies at VGAI Solutions Inc. This role is perfect for a detail-oriented engineer who thrives on optimizing high-volume manufacturing processes and wants to make a significant impact on next-generation SoC performance. Take the next step in your professional journey and apply today to join a collaborative team shaping the future of high-speed connectivity.

Quick overview

SeniorityMid Senior
Work modeOn Site
LocationSan Jose, CA, United States
Data Analysis

Job description

Senior ATE Production Test Engineer – SerDes / Co-Packaged Optics (CPO)

Location: San Jose, CA — Fully Onsite
Experience: 6+ years preferred

Role Overview

We are seeking a hands-on Production Test Engineer to develop and optimize automated test equipment (ATE) programs for SoC devices featuring SerDes interfaces and Co-Packaged Optics (CPO).

The engineer will lead production test development for wafer sort and final test, focusing on design-for-test (DFT), built-in self-test (BIST), yield optimization, test coverage, and high-volume manufacturing readiness.

Candidates must have strong practical experience in SerDes interface testing and ATE production test development, along with proficiency in Python-based automation and test data analytics. Knowledge of UCIe and PCIe protocols is also required.

Key Responsibilities

  • Develop, integrate, and maintain ATE test programs for wafer sort and final test of SoCs with SerDes and CPO interfaces.

  • Implement production test coverage for SerDes PHY features, including PRBS, loopback, margining, FEC, CDR lock, and equalization settings.

  • Use on-die BIST/DFT capabilities and ATE instrumentation to validate device functionality and electrical performance.

  • Optimize multisite testing, parallel test execution, guardbanding, test coverage, and test time to improve production efficiency and quality.

  • Correlate bench characterization results with ATE measurements, establish production limits, and support the transition from characterization to manufacturing.

  • Integrate DFT features such as scan/ATPG, boundary scan, MBIST/LBIST, and JTAG into production test flows.

  • Support pattern conversion, timing set development, pin mapping, and ATE pattern bring-up.

  • Develop UCIe- and PCIe-related production checks using firmware or test hooks, link-state verification, compliance counters, and error monitoring.

  • Build Python automation tools for ATE control, STDF data parsing, analytics, dashboards, statistical process control (SPC), and anomaly detection.

  • Collaborate with silicon design, firmware, DFT, product engineering, OSAT/probe, and signal integrity teams to troubleshoot issues and qualify engineering changes.

  • Maintain test documentation, specifications, vector maps, production limits, and release notes; support sustaining engineering and operations teams.

Required Technical Skills

1. ATE Production Test Development

  • Hands-on experience developing and debugging production test programs on ATE platforms.

  • Experience with wafer sort and final test.

  • Knowledge of timing sets, DC/AC measurements, multisite testing, and test optimization.

  • Experience with platforms such as Advantest V93K/AC+ or Teradyne UltraFLEX/UltraFLEXplus.

2. SerDes / High-Speed Interface Testing

  • Strong understanding of SerDes PHY fundamentals and high-speed chip interfaces.

  • Experience with PRBS/BER testing, loopback, margining, jitter, eye constraints, and CDR.

  • Knowledge of CTLE/DFE equalization and on-die BIST integration.

  • Understanding of FEC and high-speed interface electrical performance.

3. DFT / BIST

  • Experience with scan/ATPG patterns, boundary scan, MBIST/LBIST, and JTAG.

  • Familiarity with WGL/STIL pattern formats and production ATE pattern bring-up.

  • Ability to integrate DFT capabilities into manufacturing test flows.

4. Python Automation & Test Analytics

  • Proficiency in Python scripting for test automation and data analysis.

  • Experience parsing and analyzing STDF test data.

  • Knowledge of visualization, SPC, yield analysis, and automated anomaly detection.

  • Familiarity with MES integration and continuous integration (CI) pipelines.

5. Protocol Knowledge

  • Working knowledge of UCIe and PCIe, preferably Gen5/Gen6.

  • Understanding of production-level link checks, link-state verification, error counters, and compliance indicators.

Preferred Qualifications

  • Experience testing SoCs with Co-Packaged Optics (CPO) or optical interconnect technologies.

  • Experience translating silicon characterization results into robust, high-volume production tests.

  • Exposure to AI-assisted test development, test data triage, or automated debugging.

  • Experience with yield improvement, production quality, and manufacturing test optimization.

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