Physical Design Engineer Semiconductor / ASIC

Physical Design Engineer Semiconductor / ASIC
Location: Palo Alto, CA (100% Onsite)
Openings: 5

Job Overview

We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification.

Key Responsibilities

• Execute the complete physical design flow, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and post-route optimization.
• Perform timing analysis and achieve timing closure across multiple operating modes and process, voltage, and temperature (PVT) corners.
• Debug and resolve timing, congestion, power, signal integrity, and design variability issues.
• Perform physical verification and resolve DRC, LVS, and ERC violations.
• Conduct static timing analysis (STA) using Synopsys PrimeTime and support timing signoff.
• Analyze signal integrity, crosstalk, IR drop, and electromigration (EM) issues.
• Implement low-power design techniques, including multi-Vt, multi-voltage designs using UPF, power gating, and clock gating.
• Work on advanced technology nodes, including 7nm, 5nm, 3nm, and below.
• Collaborate with RTL, microarchitecture, DFT, CAD, and foundry teams to resolve implementation and signoff challenges.
• Develop automation scripts and improve physical design methodologies and implementation flows.

Required Qualifications

• Mandatory exposure to TSMC 2NP/3NP process technology.
• Strong hands-on experience with the complete ASIC/SoC physical design flow.
• Experience with floorplanning, power planning, placement, CTS, routing, and post-route optimization.
• Proven experience in multi-mode, multi-corner timing closure.
• Strong understanding of STA, physical verification, signal integrity, IR drop, and EM analysis.
• Experience with low-power design methodologies, including UPF, multi-Vt, multi-voltage, power gating, and clock gating.
• Experience working on advanced semiconductor process nodes, preferably 7nm, 5nm, 3nm, or below.
• Experience using industry-standard physical design and signoff tools.

Preferred Skills

• Synopsys PrimeTime for STA and timing signoff.
• Physical design implementation tools such as Synopsys ICC2 or Fusion Compiler, or Cadence Innovus.
• Signoff and physical verification tools such as Calibre or comparable solutions.
• Scripting and automation using Tcl, Python, or Perl.
• Strong debugging, problem-solving, and cross-functional collaboration skills.