STA Lead Static Timing Analysis

STA Lead Static Timing Analysis

Location: Remote
Job Type: Contract

Job Summary

We are looking for an experienced STA Lead to lead Static Timing Analysis, timing signoff, and timing closure activities for complex ASIC/SoC designs. This role will be responsible for driving timing methodology, developing and validating timing constraints, analyzing MMMC scenarios, and ensuring designs meet timing requirements through tape-out.

The ideal candidate should have strong hands-on experience with Synopsys PrimeTime, SDC constraints, timing closure, Signal Integrity (SI), crosstalk, OCV/AOCV/POCV, and Timing ECOs.

Key Responsibilities

• Lead STA methodology, timing signoff, and timing closure from block level through full-chip level.
• Develop, validate, and maintain SDC timing constraints and signoff flows.
• Perform detailed setup and hold analysis across multiple MMMC scenarios.
• Drive timing optimization and closure for complex ASIC/SoC designs.
• Perform signoff analysis using Synopsys PrimeTime, PrimeTime-SI, and PBA.
• Debug and resolve timing issues related to signal integrity, crosstalk, noise, OCV, AOCV, and POCV.
• Participate in clock architecture reviews and analyze cross-domain timing paths.
• Generate, analyze, and validate Timing ECOs to achieve timing closure.
• Support timing signoff reviews and provide timing statrecommendations for tape-out.
• Develop and maintain automation for timing analysis, reporting, and debugging using TCL and/or Python.
• Work closely with Physical Design, RTL, DFT, and other engineering teams to resolve timing issues.
• Support advanced technology-node designs and full-chip timing closure through tape-out.

Required Qualifications

• Strong hands-on experience in Static Timing Analysis (STA) and ASIC/SoC timing signoff.
• Expert-level experience with Synopsys PrimeTime.
• Experience with PrimeTime-SI and PBA.
• Strong understanding of SDC constraints and MMMC methodology.
• Hands-on experience with setup/hold analysis and timing closure.
• Strong knowledge of SI, crosstalk, noise, OCV, AOCV, and POCV.
• Experience with clock timing and cross-domain analysis.
• Strong experience with Timing ECO implementation and validation.
• Proficiency in TCL and/or Python scripting for STA automation and reporting.
• Experience supporting complex ASIC/SoC designs through timing signoff and tape-out.

Preferred Qualifications

• Experience with advanced technology nodes.
• Strong understanding of the physical design flow and timing-driven implementation.
• Experience working on full-chip designs and complete tape-out cycles.
• Experience collaborating with cross-functional ASIC/SoC design teams.