DFT (Design for Test) Engineer_SanJose, CA (Onsite)

Design for Test (DFT) Engineer
Location: San Jose, CA
Duration: 12 + Months (Potential Extension)
Interview Process: Virtual/Onsite
Rate: Up to $130/hr on W2 (No Benefits)

Job Overview

We are seeking an experienced Design for Test (DFT) Engineer to support the development and validation of next-generation semiconductor products. The role involves close collaboration with Front-End Design and Physical Design teams to implement and optimize DFT solutions for advanced wireless and connectivity chipsets.

Key Responsibilities

• Implement and validate Memory BIST solutions using Siemens Tessent.
• Perform Gate-Level Simulation (GLS) and debug simulation issues.
• Develop automation scripts using TCL, Perl, and Python.
• Work on Scan Compression methodologies including SEQ, Ultra, and TestKompress.
• Generate and debug ATPG patterns using Tetramax.
• Support ATPG diagnosis, ATE debug, silicon bring-up, and failure analysis.
• Perform DFT pattern translation using VTRAN.
• Contribute to RTL design activities using Verilog/SystemVerilog.
• Apply STA and timing analysis concepts, including CDC checks, clock gating verification, and timing constraint validation.

Required Qualifications

• 5+ years of industry experience in Design for Test (DFT).
• Strong expertise in Memory BIST, ATPG, Scan Compression, and GLS.
• Hands-on scripting experience with TCL, Perl, or Python.
• Solid debugging, problem-solving, and analytical skills.
• Ability to work independently and deliver assignments with minimal supervision.