Verification Lead - Memory Controller (CHI-G / DFI)

Location: San Jose, CA

Department: Hardware / Design Verification

Level: Lead

Experience: 10+ Years

Job Overview

We are seeking an experienced Verification Lead to own the verification strategy, planning, and execution for a Memory Controller subsystem, with strong expertise in ARM CHI-G and DFI interface verification.

The ideal candidate will lead a team of verification engineers, drive coverage closure and regression, and ensure sign-off quality for memory controller design changes.

Key Responsibilities

• Define and own the overall verification strategy and test plan for the memory controller.
• Lead development of SystemVerilog/UVM testbenches, scoreboards, checkers, and verification environments.
• Verify ARM CHI-G coherency, including request/response/snoop behavior, ordering, and coherency scenarios.
• Verify DFI-compliant PHY interfaces, including command/data timing and calibration sequences.
• Drive functional, code, and assertion coverage closure.
• Coordinate with RTL design teams to understand design changes and update verification plans and regression suites.
• Develop and execute formal verification strategies for protocol-critical paths where applicable.
• Manage regressions, triage failures, and drive bug closure with Design and DFT teams.
• Lead, mentor, and review the work of verification engineers.
• Report verification status, risks, and schedule to program management and cross-functional teams.
• Own verification documentation, including test plans, coverage models, and sign-off reports.
• Support verification activities through tapeout and sign-off.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of Design Verification experience.
• 3+ years in a Verification Lead or management capacity.
• Strong hands-on experience verifying DDR4/DDR5/LPDDR memory controllers.
• Deep knowledge of ARM CHI/CHI-G protocol verification, including coherency, snoop filtering, and ordering.
• Experience verifying DFI-compliant PHY interfaces.
• Expert-level SystemVerilog and UVM skills.
• Experience building or significantly extending UVM verification environments.
• Experience with APB, AHB, AXI4, and/or ACE interfaces.
• Strong experience with coverage-driven verification and sign-off processes.
• Proven experience leading verification teams through tapeout.

Preferred Qualifications

• Experience with formal verification tools for protocol and coherency checking.
• Experience correlating pre-silicon verification with post-silicon validation.
• Exposure to AI/LLM-assisted verification tools for test generation, coverage analysis, or debug.

How to Apply

Interested candidates can send their updated resume to:

Subject: Verification Lead - Memory Controller