Physical Design Engineer

We are seeking a highly skilled Physical Design Engineer to drive block-level implementation and optimization activities for advanced ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flow, timing, power, area optimization, and tape-out support.

Required Qualifications:

• Strong understanding of ASIC physical design and implementation flow.

• Hands-on experience with Synopsys Fusion Compiler.

• Experience in floorplanning, placement, CTS, routing, and ECO implementation.

• Knowledge of timing analysis fundamentals and timing closure methodologies.

• Understanding of congestion management, utilization optimization, and routing concepts.

• Familiarity with LEF/DEF, Liberty, Verilog, and standard physical design file formats.

• Basic understanding of IR Drop, EM analysis, and Physical Verification flows.

• Strong scripting skills in TCL, Perl, and/or Python.

• Excellent debugging, problem-solving, and teamwork skills.

Preferred Qualifications:

• Experience with advanced technology nodes and full-chip implementation.

• Exposure to signoff tools, DFM methodologies, and successful tape-out cycles.