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DESIGN VERIFICATION ENGINEER

SUNRAY INFORMATICSSunnyvale, CA🇺🇸United States

Quick overview

SeniorityMid Senior
Work modeOn Site
LocationSunnyvale, CA, United States
Verilog

Job description

Hiring: Design Verification Engineer

Location: Sunnyvale, CA 94086 (Onsite)
Full-Time | W2 Only
Interview: Webcam

Client: META

We are seeking an experienced Design Verification Engineer with 10+ years of experience and strong expertise in System Verilog, UVM/OVM, and Verilog. The ideal candidate should have hands-on experience in IP, Sub-system, and SoC-level verification of complex digital designs, along with strong skills in functional verification, testbench development, debugging, and coverage-driven verification.

Complete job details will be shared directly with the consultant.

If you have any questions, feel free to reach out via email. We look forward to your response.

Regards,

Madhu

(445) (400) (2863) (No calls please)

madhu at sunrayinformatics dot com

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